// -*- mode:c++ -*-

// Copyright (c) 2011 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

def template BranchImm64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, int64_t _imm);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchImm64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template BranchImmCond64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, int64_t _imm,
                   ConditionCode _condCode);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchImmCond64Constructor {{
    %(class_name)s::%(class_name)s(
            ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _condCode)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template BranchReg64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _op1);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchReg64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template BranchRegReg64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchRegReg64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
                                   RegIndex _op2) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template BranchImmReg64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, int64_t imm, RegIndex _op1);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchImmReg64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm,
                                   RegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};

def template BranchImmImmReg64Declare {{
class %(class_name)s : public %(base_class)s
{
  private:
    %(reg_idx_arr_decl)s;

  public:
    // Constructor
    %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
                   RegIndex _op1);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};

def template BranchImmImmReg64Constructor {{
    %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                   int64_t _imm1, int64_t _imm2,
                                   RegIndex _op1) :
        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                       _imm1, _imm2, _op1)
    {
        %(set_reg_idx_arr)s;
        %(constructor)s;
    }
}};
